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| Freescale Semiconductor Technical Data MC100ES6210 Rev 3, 02/2005 Low Voltage 2.5/3.3 V Differential ECL/PECL/HSTL Fanout Buffer The MC100ES6210 is a bipolar monolithic differential clock fanout buffer. Designed for most demanding clock distribution systems, the MC100ES6210 supports various applications that require to distribute precisely aligned differential clock signals. Using SiGe technology and a fully differential architecture, the device offers very low clock skew outputs and superior digital signal characteristics. Target applications for this clock driver is high performance clock distribution in computing, networking and telecommunication systems. Features * * * * * * * * * * * * Dual 1:5 differential clock distribution 30 ps maximum device skew Fully differential architecture from input to all outputs SiGe technology supports near-zero output skew Supports DC to 3 GHz operation of clock or data signals ECL/PECL compatible differential clock outputs ECL/PECL compatible differential clock inputs Single 3.3 V, -3.3 V, 2.5 V or -2.5 V supply Standard 32 lead LQFP package Industrial temperature range Pin and function compatible to the MC100EP210 32-lead Pb-free Package Available MC100ES6210 LOW VOLTAGE DUAL 1:5 DIFFERENTIAL PECL/ECL/HSTL CLOCK FANOUT BUFFER FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-03 AC SUFFIX 32-LEAD LQFP PACKAGE Pb-FREE PACKAGE CASE 873A-03 Functional Description The MC100ES6210 is designed for low skew clock distribution systems and supports clock frequencies up to 3 GHz. The device consists of two independent 1:5 clock fanout buffers. The input signal of each fanout buffer is distributed to five identical, differential ECL/PECL outputs. Both CLKA and CLKB inputs can be driven by ECL/PECL compatible signals. If VBB is connected to the CLKA or CLKB input and bypassed to GND by a 10 nF capacitor, the MC100ES6210 can be driven by single-ended ECL/PECL signals utilizing the VBB bias voltage output. In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even if only one output is used. In the case where not all ten outputs are used, the output pairs on the same package side as the parts being used on that side should be terminated. The MC100ES6210 can be operated from a single 3.3 V or 2.5 V supply. As most other ECL compatible devices, the MC100ES6210 supports positive (PECL) and negative (ECL) supplies. The is function and pin compatible to the MC100EP210. (c) Freescale Semiconductor, Inc., 2005. All rights reserved. QA4 QA3 QA3 AQ4 QB0 QB0 QB1 18 VCC CLKA CLKA QA1 QA1 QA2 QA2 QA3 QA3 QA4 QA4 QB0 QB0 QB1 QB1 QB2 QB2 QB3 QB3 QB4 QB4 24 23 22 21 20 19 QB1 17 16 15 14 QA0 QA0 VCC Q2 Q2 Q1 Q1 Q0 Q0 VCC 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 VCC QB2 QB2 QB3 QB3 QB4 QB4 VCC VCC CLKB CLKB MC100ES6210 13 12 11 10 9 CLKA CLKB CLKB N.C. CLKA VBB Figure 1. MC100ES6210 Logic Diagram Table 1. Pin Configuration Pin CLKA, CLKA CLKB, CLKB QA[0-4], QA[0-4] QB[0-4], QB[0-4] VEE(1) VCC VBB Input Input Output Output Supply Supply Output DC I/O Type ECL/PECL ECL/PECL ECL/PECL ECL/PECL Figure 2. 32-Lead Package Pinout (Top View) VCC Function Differential reference clock signal input (fanout buffer A) Differential reference clock signal input (fanout buffer B) Differential clock outputs (fanout buffer A) Differential clock outputs (fanout buffer B) Negative power supply Positive power supply. All VCC pins must be connected to the positive power supply for correct DC and AC operation. Reference voltage output for single ended ECL or PECL operation 1. In ECL mode (negative power supply mode), VEE is either -3.3 V or -2.5 V and VCC is connected to GND (0 V). In PECL mode (positive power supply mode), VEE is connected to GND (0 V) and VCC is either +3.3 V or +2.5 V. In both modes, the input and output levels are referenced to the most positive supply (VCC) Table 2. Absolute Maximum Ratings(1) Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 3.6 VCC + 0.3 VCC + 0.3 20 50 125 Unit V V V mA mA C Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. MC100ES6210 2 Advanced Clock Drivers Devices Freescale Semiconductor VEE VBB Table 3. General Specifications Symbol VTT MM HBM CDM LU CIN JA Characteristics Output Termination Voltage ESD Protection (Machine Model) ESD Protection (Human Body Model) ESD Protection (Charged Device Model) Latch-Up Immunity Input Capacitance Thermal Resistance Junction to Ambient JESD 51-3, single layer test board 200 4.0 83.1 73.3 68.9 63.8 57.4 59.0 54.4 52.5 50.4 47.8 23.0 86.0 75.4 70.9 65.3 59.6 60.6 55.7 53.8 51.5 48.8 26.3 110 200 2000 Min Typ VCC - 2(1) Max Unit V V V V mA pF C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C Inputs Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min MIL-SPEC 883E Method 1012.1 Condition JESD 51-6, 2S2P multilayer test board JC TJ Thermal Resistance Junction to Case Operating Junction Temperature(2) (continuous operation) MTBF = 9.1 years 1. Output termination voltage VTT = 0 V for VCC = 2.5 V operation is supported but the power consumption of the device will increase. 2. Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should be selected according to the application life time requirements (See application note AN1545 for more information). The device AC and DC parameters are specified up to 110C junction temperature allowing the MC100ES6210 to be used in applications requiring industrial temperature range. It is recommended that users of the MC100ES6210 employ thermal modeling analysis to assist in applying the junction temperature specifications to their particular application. Table 4. PECL DC Characteristics (VCC = 2.5 V 5% or VCC = 3.3 V 5%, VEE = GND, TJ = 0C to +110C) Symbol Characteristics Differential Input Voltage(1) Differential Cross Point Voltage(2) Input Current(1) Min Typ Max Unit Condition Clock Input Pair CLKA, CLKA, CLKB, CLKB (PECL differential signals) VPP VCMR IIN VOH VOL 0.1 1.0 1.3 VCC - 0.3 100 V V A Differential operation Differential operation VIN = VIL or VIN = VIH IOH = -30 mA(3) IOL = -5 mA(3) PECL Clock Outputs (QA0-4, QA0-4, QB0-4, QB0-4) Output High Voltage Output Low Voltage VCC = 3.3 V5% VCC = 2.5 V5% VCC -1.2 VCC -1.9 VCC -1.9 VCC -1.005 VCC -1.705 VCC -1.705 60 VCC -1.38 VCC -1.26 VCC -0.7 VCC -1.5 VCC -1.3 100 VCC -1.14 V V Supply Current and VBB IEE VBB Maximum Quiescent Supply Current without Output Termination Current Output Reference Voltage mA V VEE pin IBB = 0.2 mA 1. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 2. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. 3. Equivalent to a termination of 50 to VTT. MC100ES6210 Advanced Clock Drivers Devices Freescale Semiconductor 3 Table 5. ECL DC Characteristics (VEE = -2.5 V 5% or VEE = -3.3 V 5%, VCC = GND, TJ = 0C to +110C) Symbol Characteristics Differential Input Voltage(1) Differential Cross Point Input Current(1) Voltage(2) Min Typ Max Unit Condition Clock Input Pair CLKA, CLKA, CLKB, CLKB (ECL differential signals) VPP VCMR IIN VOH VOL 0.1 VEE + 1.0 1.3 -0.3 100 V V A Differential operation Differential operation VIN = VIL or VIN = VIH IOH = -30 mA(3) IOL = -5 mA(3) ECL Clock Outputs (QA0-4, QA0-4, QB0-4, QB0-4) Output High Voltage Output Low Voltage VCC = 3.3 V 5% VCC = 2.5 V 5% -1.2 -1.9 -1.9 -1.005 -1.705 -1.705 -0.7 -1.5 -1.3 V V Supply Current and VBB IEE VBB Maximum Quiescent Supply Current without Output Termination Current Output Reference Voltage -1.38 60 -1.26 100 -1.14 mA V VEE pin IBB = 0.2 mA 1. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 2. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. 3. Equivalent to a termination of 50 to VTT. MC100ES6210 4 Advanced Clock Drivers Devices Freescale Semiconductor Table 6. AC Characteristics (ECL: VEE = -3.3 V 5% or VEE = -2.5 V 5%, VCC = GND) or (PECL: VCC = 3.3 V 5% or VCC = 2.5 V 5%, VEE = GND, TJ = 0C to +110C)(1) (2) Symbol Characteristics Differential Input Voltage(3) (peak-to-peak) Differential Input Crosspoint Voltage (4) Min Typ Max Unit Condition Clock Input Pair CLKA, CLKA, CLKB, CLKB (PECL or ECL differential signals) VPP VCMR 0.3 PECL ECL 1.2 VEE + 1.2 0 175 260 0.3 1.3 VCC - 0.3 -0.3 V V V V ECL Clock Outputs (Q0-9, Q0-9) fCLK tPD VO(P-P) Input Frequency Propagation Delay CLKA to QAx or CLKB to QBx Differential Output Voltage (peak-to-peak) fO < 1.1 GHz fO < 2.5 GHz fO < 3.0 GHz Output-to-Output Skew (per bank) Output-to-Output Skew (part-to-part) Output Cycle-to-Cycle Jitter Output Pulse Skew Output Duty Cycle Output Rise/Fall Time (5) 3000 350 MHz ps Differential Differential 0.45 0.35 0.20 0.70 0.55 0.35 13 30 175 1 50 V V V ps ps ps ps % % ps DCREF = 50% DCREF = 50% 20% to 80% Differential Differential tsk(O) tsk(PP) tJIT(CC) tSK(P) DCQ tr, tf fREF < 0.1 GHz fREF < 1.0 GHz 49.5 45.0 30 50 50 50.5 55.0 250 1. AC characteristics are design targets and pending characterization. 2. AC characteristics apply for parallel output termination of 50 to VTT. 3. VPP (AC) is the minimum differential ECL/PECL input voltage swing required to maintain AC characteristics including tPD and device-to-device skew. 4. VCMR (AC) is the crosspoint of the differential ECL/PECL input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC) range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation delay, device and part-to-part skew. 5. Output pulse skew is the absolute difference of the propagation delay times: | tPLH - tPHL |. Differential Pulse Generator Z = 50 ZO = 50 ZO = 50 RT = 50 VTT DUT MC100ES6210 RT = 50 VTT Figure 3. MC100ES6210 AC Test Reference MC100ES6210 Advanced Clock Drivers Devices Freescale Semiconductor 5 PACKAGE DIMENSIONS 4X 6 D1 PIN 1 INDEX 0.20 H A-B D e/2 3 A, B, D D1/2 32 25 1 E1/2 A 6 E1 DETAIL G 8 B E E/2 4 F F 17 DETAIL G NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DATUMS A, B, AND D TO BE DETERMINED AT DATUM PLANE H. 4. DIMENSIONS D AND E TO BE DETERMINED AT SEATING PLANE C. 5. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM b DIMENSION BY MORE THAN 0.08-mm. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION: 0.07-mm. 6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25-mm PER SIDE. D1 AND E1 ARE MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING MOLD MISMATCH. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.1-mm AND 0.25-mm FROM THE LEAD TIP. 7 9 D D 4 D/2 4X 0.20 C A-B D H 28X e 32X 0.1 C SEATING PLANE C DETAIL AD PLATING BASE METAL b1 c c1 b 8X 5 8 (1) R R2 R R1 0.20 M C A-B D SECTION F-F A A2 0.25 GAUGE PLANE A1 (S) (L1) L DETAIL AD DIM A A1 A2 b b1 c c1 D D1 e E E1 L L1 q q1 R1 R2 S MILLIMETERS MIN MAX 1.40 1.60 0.05 0.15 1.35 1.45 0.30 0.45 0.30 0.40 0.09 0.20 0.09 0.16 9.00 BSC 7.00 BSC 0.80 BSC 9.00 BSC 7.00 BSC 0.50 0.70 1.00 REF 0 7 12 REF 0.08 0.20 0.08 --0.20 REF CASE 873A-03 ISSUE B 32-LEAD LQFP PACKAGE MC100ES6210 6 Advanced Clock Drivers Devices Freescale Semiconductor NOTES MC100ES6210 Advanced Clock Drivers Devices Freescale Semiconductor 7 How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. (c) Freescale Semiconductor, Inc. 2005. All rights reserved. MC100ES6210 Rev. 3 02/2005 |
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